The present invention relates to a wafer level package technique and, more particularly, to a wafer level package structure of micro electromechanical devices.
In the semiconductor industry, the micro-machining technology is a newly developing technique. It exploits the integrated-circuit (IC) technology to fabricate various kinds of micro-sensors and micro-drivers. Additionally, the micro-machining technology integrated with micro-electronic circuits can constitute micro-systems, which is called micro electromechanical system (MEMS).
Different from the conventional IC fabrication technology, the fabrication technology relevant to micro electromechanical devices is very broad and complex. However, most micro electromechanical devices make use of the micro-machining technology to fabricate suspended structures having only a few supporting points so as to enhance mechanical sensitivity thereof (e.g., pressure sensors), or to reduce thermal conductance thereof (e.g., thermal sensors). In the conventional fabrication process of IC devices, after IC devices are fabricated on a wafer, the wafer is diced into a plurality of single chips, which then undergo the procedures of wire bonding and compound molding for packaging.
In consideration of cost, the MEMS industry will be benefited if the IC fabrication process can apply to the production of micro electromechanical devices. However, some difficulties must be overcome. First, the flushing of cooling water during the dicing procedure and the small powders resulted from dicing will damage suspended devices so that the yield will be reduced. Secondly, micro electromechanical devices will be fixed during the procedure of compound molding so that the object of enhancing their sensitivity by suspended structures will be lost.
Accordingly, the present invention aims to propose a package structure applicable to micro electromechanical devices so as to avoid damage in the above packaging procedure.
The primary object of the present invention is to propose a wafer level package of micro electromechanical devices so that damage of the micro electromechanical devices due to external forces in the packaging procedure can be avoided.
Another object of the present invention is to use a silicon wafer as a package base so that the whole package device not only has good evenness and keeps good contact with a chip, but also has better thermal conductance. Packaged modules will thus have good heat-radiating effect.
According to an embodiment of the present invention, a wafer having a plurality of micro electromechanical devices and a package wafer base of the same size are installed together. Conductor plugs between the upper and lower surfaces of the package wafer are exploited to conduct the upper and lower surfaces of the package wafer. Solder bumps are then disposed at two ends of the conductor plugs. The solder bumps are installed on predetermined solder bumps on the micro electromechanical device wafer. Electric connection can thus be achieved between the micro electromechanical device wafer and the package wafer.
Besides, according to another embodiment of the present invention, a plurality of micro electromechanical devices are fabricated on a package wafer base, which is then installed with a substrate of the same size. Conductor plugs between the upper and lower surfaces of the package wafer are exploited to conduct the upper and lower surfaces of the package wafer. Next, solder bumps are disposed at two ends of the conductor plugs. The solder bumps are then installed on predetermined solder bumps on the substrate.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which: